Resumen

COCA, Ledys; FRANCO, Zulay  y  PATETI, Antonio. IMPLEMENTATION OF MORPHOLOGICAL FILTERS USED IN THE PROCESSING OF DIGITAL IMAGES IN A PROGRAMMABLE LOGIC DEVICE. uct [online]. 2008, vol.12, n.48, pp.171-182. ISSN 1316-4821.

We present the implementation on a programmable logic device (PLD) morphological filters used for noise reduction and detection of edges in a digital image. The programmable logic device used is the FPGA Virtex XCV-800 embedded in the board development XSV-800 fabricated for the company XESS Corp. and the second part of the design is the one that corresponds to the VHDL description of the components to be implemented in the FPGA. The morphological filters were implemented efficiently in the FPGA, because these devices allow processing run concurrently. The choice of filters morphological undoubtedly was the most successful and can be used instead of the standard linear filters, as long as the filters tend to distort the linear geometry of the underlying image, morphological generally leave intact. The results obtained in the processing of the images were entirely satisfactory in terms of resolution, sharpness and image quality.

Palabras clave : Morphological Filters; Digital Processing Image; VHDL; FPGA.